Richards
superconductive storage circuits



NOV. 4, 1969 N RlCHARDs Re. 26,702

SUPERGONDUCIIVE STORAGE CIRCULI'S Original Filsd Feb. 18, 1964 4 Sheets-Sheet 1 WORD F |G.2. A

l N V E N TO R NORMAN 0. RICHARDS BY M I lk mENT NOV 4, 1969 RICHARDS Re. 26,702

SUPERCONDUCTIVE STORAGE CIRCUITS Original Filed Feb. 18, 1964 4 Sheets-Sheet 2 D I GI T DRIVER i DRIVER, PRIMARY SEE EI R PLATE READ SENSE V G SECONDARY STORE ATE AMPLIFIER PLATE SELECTOR II ADDRESS READ GATE SELECTOR DRIVER LW E CW LH I 6W LL INVENTOR NORMAN D. RICHARDS M K AGENT N 4. 1969 N. 0. RICHARDS SUPERCONDUCTIVE STORAGE CIRCUITS 4 Sheets-Sheet .1

Original Filed Feb. 18, 1964 5 G. 4 0 Q Q a ll 4 s F 0/ H m m Q w A. 2 RM 03/? 4 o MAI:v will: U1 i.-. -l a o m Q 37 m F: D. M H% YC "M M 4 J m b n 2 9 4 RN M m w w W M n J r!l l F .8 a7 a 1 c 2 U1. 2 2 3 H. W 6 T 8 a a 3 3 w TO c .D c TC 6 AGENT Nov. 4, 1969 N. D. RICHARDS 25,702

SUFERCONDUCTIVZI STORAGE CIRCUITS Original Filed Feb. 18, 1964 FIG. 6.

4 Sheets-Sheet ADDRESS I CURRENT WORD CURRENT DIGIT CURRENT STORAGE CELL VOLTAGE CURRENT AMPLIFIER WRITE GATE I I INPUT l I 1 I I 4 I I U I I I I I l l l I 9 I; E m cc 3 Q; E

INVENTOR NORMAN D. RICHARDS LCM/2L /& .Lyi

AGENT United States Patent 26,702 SUPERCONDUCTIVE STORAGE CIRCUITS Norman Dennis Richards, Tilgate, Crawley, Sussex, England, assignor to US. Philips Corporation, New York,

N.Y., a corporation of Delaware Original No. 3,362,018, dated Jan. 2, 1968, Ser. No.

345,700, Feb. 18, 1964. Application for reissue Oct. 2,

1968, Ser. No. 769,455

Int. Cl. Gllb 9/00; H031: 17/00 I US. Cl. 340173.1 16 Claims Matter enclosed in heavy brackets appears in the original patent but forms no part of this reissue specification; matter printed in italics indicates the additions made by reissue.

ABSTRACT OF THE DISCLOSURE The invention is a superconductive storage matrix which uses a group of series connected superconductive storage elements and a pair of superconductive devices connected across the elements and bistably switched between a normal characteristic impedance and zero impedance in response to a corresponding pair of input signats. A proper selection of the input signals to the superconductive devices determines whether the information associated with the matrix is to be stored or read out.

This invention relates to electric circuits employing superconducting elements such as cryotrons.

Such a circuit may form part of a computer using superconductive elements as the storage elements.

By combining the advantages of compactness and relatively simple construction of a superconductive storage matrix with the flexibility and speed of operation of external amplifiers and driving circuits, a relatively compact and economical computer may be designed.

Irrespective of the manner of organization of the store, means must be provided to specify the store address and to set the individual bits in the word. Also, amplifiers must be provided for the output of the store. With a superconductive storage matrix it is essential to provide cooling apparatus at an irreducible minimum cost and so it is little more expensive to provide a very large store of say l0 bits than a small store.

There are basically two types of superconductive current stores. The first of these types is typlificd by the Crowe cell or the R.C.A. continuous sheet store which operates on a coincident current mode and stores information by means of induced persistent currents. The second type operates on a word address mode and relies on the logical switching properties of cryotrons to store a current that is defined by an external circuit and is typified by the store described by Haynes of IBM in Solid State Electronics 1 (1960), page 399.

It is an object of the present invention to provide an electric circuit for a computer using superconductive storage elements in which the signal to noise ratio can be substantially improved.

According to one aspect of the present invention there is provided an electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point; a first superconductivc device is connected between a first terminal and a second terminal and is arranged to be switched in a bistable manner, between a condition of zero impedance and a condition of normal characteristic impedance, in dependence upon a first input signal which is arranged to be applied to the superconductive device. The first terminal is connected to said first point of the series connected superconductive storage elements and the second Re. 26,702 Reissued Nov. 4, 1969 ice terminal is connected to said second point of the series connected storage elements.

According to another aspect of the invention, the circuit may include a third and a fourth terminal between which is connected a second superconductive device which is arranged to be switched in a bistable manner between a normal characteristic impedance and zero impedance, in dependence upon a second input signal which is arranged to be applied to the second superconductive device, said third terminal being connected to said second point and said fourth terminal being connected to said second terminal.

One embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

FIGURE 1 shows the symbol for a storage element;

FIGURE 2 shown a plurality of such storage elements connected according to the invention;

FIGURE 3 shows the drive arrangements and sense arrangement for a superconductive store;

FIGURE 4 shows the relative dimensions of the conductors of a storage element;

FIGURE 5 shows a 16 bit superconductive store and a superconductive address selection tree; and

FIGURE 6 shows the pulse sequence for storage and sensing.

Referring now to the drawings, FIGURE 1 represents a storage element of the type described in my co-pending U.S.A. patent application Ser. No. 345,699 filed Feb. 18, 1964 for Superconductive Devices. Essentially the storage element comprises a gate conductor 1 composed pref erably of tin, crossed at right angles by a control conductor 2 composed preferably of lead. A loop 3, also preferably of lead, is connected to the gate conductor 1 on both sides of the switched region 4. The loop 3 is uninfluenced by current flowing in the control conductor 2 and remains superconductive. The control conductor 2 is insulated from the gate conductor 1 and the loop 3 by a thin insulating layer preferably of silicon monoxide.

Assume that the device is cooled sufficiently so that the conductors are superconductive and a current is caused to flow in the gate conductor 1; then if a current is applied to the control conductor 2 so as to cause the region 4 to become normally conductive, the current originally flowing in the gate conductor 1 will be diverted into the superconductive loop 3. If now the current in the control conductor 2 is removed, thus causing the region 4 to become superconductive again, and the current in the gate conductor 1 is also removed, this may be considered as applying an equal but opposite current to the gate conductor 1, and a circulating current will be set up through the loop 3 and superconductive region 4 of the gate conductor 1. This circulating current is equal in magnitude to the original current in the gate conductor 1. The current will continue to circulate around the loop and its magnitude will be unaffected providing the path through which it travels remains superconductive. This arrangement is therefore an analogue storage element provided that the critical current for any of the materials of the element is not exceeded by the storage current. It will be appreciated that the current may circulate in either direction dependent upon the direction of the original current in the gate conductor 1.

The stored current may be sensed by applying a current to the control conductor 2 so as to switch the region 4 into the normally conductive state and sensing the voltage drop across the region 4. This is a form of destructive read out since once the region 4 is normally conduclive, therefore possessing predetermined resistance, the current in the loop will decay to zero.

Referring now to FIGURE 2 which shows four storage elements, 5, 6, 7, and 8 connected in series between terminals 9 and 10. The storage elements 5, 6, 7 and 8 are traversed by control conductors 11, 12, 13 and 14 respectively. A cryotron device 15, which may be an in line" cryotron or a multiple crossing crossed firm cryotron, has its gate conductor connected between the terminal 9 and a terminal 16. As similar cryotron device 17 has its gate conductor connected between the terminal and a terminal 18, which is directly connected by Way of the conductor 19 to the conductor 16. The cryotron devices 15 and 17 are controlled by currents in control conductors and 21 respectively.

In operation, when a current is required to be stored in one of the elements, say the storage element 6, a current is applied to the control conductors l2 and 21, and the storage current is applied to the terminal 10. The storage current passes through the storage elements 8 and 7, then as the gate of the storage element 6 is normally conductive, the storage current flows through the superconductive by-pass loop of the storage element 6 and then through the storage element 5. As the cryotron device 15 is in the superconductive state, the storage current will return to the terminal 18 via the device 15 and the conductor 19. The conductor 19 may be ground, a ground plane, or a conductor laid down by vapour deposition using a conventional mask. As the cryotron device 15 efiectively short circuits the terminals 9 and 16, no output will appear across these terminals.

In a computer, there will generally be considerably more than four storage elements in each line and the time of transmission of pulses, the matching of the line and ways of obtaining maximum power output from the line will have to be considered. When there is an input across the terminals 10 and 18 the cryotron device 15 is super- 1 conductive and the cryotron device 17 is normally conductive. Preferably the device 17, when normally conductive, has an impedance equal to the impedance of the line.

During read out of the current stored in the element 6, the device 17 is superconductive and a current is applied to the control conductor 20 so as to switch the gate normal and apply the characteristic impedance of the line between the terminals 9 and 16. A current is then applied to the control conductor 12 to switch the gate conductor of the element 6 normal. The storage current circulating in the element 6 will then decay and can be detected across the output terminals 9 and 16.

FIGURE 3 shows the general organisation of a 25,600 word and 1.28 megabit store, with an access time of approximately 3 ,uSCCOnds and a cycle time of about It) tseconds.

Reference is now made to FIGURE 5 which shows a storage plate containing only 16 storage elements whereas a plate containing 1,280 bits is required for the computer shown in FIGURE 3. The circuit of FIGURE 5 generally comprises an address selection section 22 and a storage matrix section 23.

The address selection section 22 comprises a number of crossed film cryotrons connected in a known manner in the form of a selection tree. An input terminal 24 is connected to the gate conductors of cryotrons 25 and 26 which are driven from control conductors 27 and 28 respectively. The output from the gate of the cryotrons 25 is connected to the gate conductors of cryotrons 29 and 30 which are driven from control conductors 31 and 32 respectively. The output from the gate of the cryotron 26 is connected to the gate conductors of cryotrons 33 and 34 which are driven from the control conductors 31 and 32 respectively.

The storage matrix section 23 comprises 16 storage elements which are referenced on a co-ordinate system. The four rows are referenced a, b, c and d and the four columns referenced A, B, C and D so that a storage element in the second row and third column is referenced bC.

Input cryotrons 35, 36, 37 and 38 are connected across the inputs to the rows a, b, c and d respectively and the input cryotrons 35, 36, 37 and 38 are driven from a common control conductor 39. Output cryotrons 40, 41, 42 and 43 are connected across the output of the rows a, b, c and d respectively and are driven from a common control conductor 44.

Referring now to FIGURES 5 and 6, if it is required to write the digit 1 in the element bC then the output cryotrons 40, 41, 42 and 43 are superconductive and hence short the output, the address current is applied to the control conductors 28 and 32.

The address current renders the cryotrons 26 and 30 and 34 normally conductive and so leaves the superconductive paths from the terminal 24 through the cryotrons 25 and 29 to the column C. The normally conductive cryotrons 26, 30 and 34 prevent current from passing down the conductors A, B and D. The write gate current is applied to the control conductor 39 so rendering the input cryotrons 35, 36, 37 and 38 normally conductive, the word current is applied to the row b and the digit current is applied to the terminal 24. A persistent current is thereby set up in the storage element bC.

To sense the current set up in the storage element bC the same address cryotrons are selected as above, the output cryotron 41 is rendered resistive by the read gate current applied to the control conductor 44 and the input cryotron 36 is superconductive as no current is applied to the control conductor 39. The word current applied to the terminal 24 switches the gate of the storage element bC.

To sense the current set up in the storage element bC the same address cryotrons are selected as above, the output cryotron 41 is rendered resistive by the read gate current applied to the control conductor 44 and the input cryotron 36 is superconductive as no current is applied to the control conductor 39. The word current applied to the terminal 24 switches the gate of the storage element bC from the superconductive state to the resistive state and so the storage cell current causes a voltage drop across the gate. This voltage will only be a transient voltage as the current will decay with a time constant determined by the L/R ratio of the loop. The voltage across the gate of the element bC is detected by an external amplifier connected to the digit conductor. Because the digit conductors are common to the reading and writing circuits, the input cryotrons serve to isolate the writing circuits during reading and the output cryotrons are controlled to isolate the sense amplifiers during writing. The impedance of the input and output cryotrons when they are switched to the normally conductive state, are arranged to be equal to the characteristic impedance of the storage line.

Considering the following basic cryotron parameters:

Tin gates 0.5 1 thick and operated at 34 K. Average conductor/ground plane spacing: 1,1. Conductor inductance 1.2)(10- H per square Gate resistivity, R =4 per square Gate external critical field, H =50 A./cm. Gate internal critical field, H =27.5 A./cm. Efficiency E=H /H =0.55

It will be appreciated that to allow for tolerances the actual current stored in the gate will be reduced by a suitable factor, say 30%, and the word current would be increased by a similar proportion.

With a width of control conductor 100a then i =0.S amp and the output voltage=0.7 0.5 2 10" For an integrating amplifier i.e. if the pulse is short compared with the amplifier risetime the important parameter is fVdt=L i where L =inductance of the storage element It is thus advantageous to make L as high as possible provided that L /R is not so long as to limit the cycle time.

Referring now also to FIGURE 4 which shows the form of layout of a suitable storage element the width GW of the gate conductor is 200 the width LW of the loop conductor is 100 .1 and the width CW of the control conductor is 100/L. The length LL of one side of the loop is 500 and the length LI-l of the adjacent side of the loop is 500 For a storage element as shown in FIGURE 4 with the above dimensions then:

Loop inductance=20 1.2 l0- H Gate resistance=2 l0- ohms L /R 12 X l0 secs.

If the cell inductance is increased by providing a hole in the ground plane, as described in my above referred to co-pending patent application, the inductance may be increased by about 100 times and so L /R ratios of up to one asecond can be obtained.

The digit current required=l =0.7 0.02 27 =0.38 amp and the word current required =I =0.7 amp.

The selection of word conductors and bits has been described with reference to FIGURES and 6, however, considering the case of 256 words per plate and each word containing 50 bits, if the bits are spaced at 1 mm. intervals along the word conductor the inductance of the word is L If crossed film cryotrons are used in the address selection section, the crossing ratio of each cryotron is unity.

If E=0.55 then the address eurrents=%l Calculated minimum address current=0.7/0.55=l.3

amps.

However, to allow for tolerances, a factor of two should be included so that the address circuit I,,=2.6 amps. As the address cryotrons are connected in the form of a tree which has the effect of decreasing the impedance for a 256 way switch, the effective resistance is about R,/10=0.4 mohms. The time for the current to reach equilibrium is about 2L/R and therefore the switching time for an external current pulse 3n sees.

line and increase the delay. It will also produce a low pass filter network with a given cut-off frequency.

The evaporated conductor will have an inductance per unit length equal to that of an air spaced line of Z =377/200- -1.88Q.

The interconnection between plates has an inductance per unit length equal to that of line of Z =l00S2. The length of the interconnection will only be about 2 mm. compared with 10 cm. of line on the plate and so the additional inductance due to plate interconnections will be about equal to the plate line inductance. This will raise the impedance of the composite line to 1.4 times its original value and increase the delay by the same factor. The cut off frequency of the composite line will be high enough to be neglected.

The total delay down such a line depends upon its length and the velocity of propagation of pulses along the line. If the dielectric constant of the silicon monoxide is 8 and the additional lumped inductance is equal to the distributed inductance the velocity along the line will be 0.25 that in free space. The length of line for plates would be 100 x 10 cm. i.e. 10 metres. Thus the delay in the sense line would be 4X3.3 l0=l30 msec.

The Z of the line would be about 0.99.

The line is terminated by a cryotron having a normal resistance equal to 900 m9. As previously described this may be switched so as to short circuit the read amplifier except during the read period. The length to width ratio r of this cryotron depends upon Ra. If Ra is 4 mil then Cryotron length=0.2 x 225:4.5 cm.

(The voltage V across the terminating resistor when in the superconduction state will be di L The inductance of such a cryotron would be L =225X 1.2 X10" =2.7 10 1-1 If the rise time of the digit current is 0.l/nsecond and its magnitude is 400 ma. then di /dt=0.4 l0

As this is little greater than the sense output it may easily be rejected by a time strobe. If the sense amplifier is effectively an integrating amplifier it is more useful to consider the ratio of the product Li for the switched storage element and the digit current interference. As the current is the same in both cases, the ratio is simply the ratio of inductances. For the storage element without holes in the ground plane the integrated interference voltage would be about 10 times greater than the integrated storage element voltage, but for the storage element with a hole in the ground plane the integrated interference voltage would be about 10 times less than the integrated signal voltage. The far end of the line can either be permanently terminated with a suitable resistance, or preferably, it is terminated by a similar cyrotron which is controlled by the complement of the first cyrotron control current.

While the invention has been described with respect to specific embodiments, it is susceptible to modifications and variations by those skilled in the art without departing from the inventive concept as set forth in the claims.

What I claim is:

1. A superconductive storage circuit comprising: a plurality of superconductive storage elements connected in series between a first point and a second point, a first superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first superconductive device in a bistable manner between a condition of zero impedance and the condition of normal characteristic impedance, said first terminal being connected to said first point and said second terminal being connected to said second point of the series connected storage elements.

2. A superconductive storage circuit comprising: a plurality of superconductive storage elements connected in series between a first point and a second point, a first superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first superconductive device in a bistable manner between a condition of zero impedance and the condition of normal characteristic impedance, said first terminal being connected to said first point of the series connected storage elements [An electric circuit as claimed in claim 1, further including] a third terminal and a fourth terminal, a second superconductive device connected between said third and fourth terminals, means for applying a second input signal to said second superconductive device, said second input signal acting to switch said second superconductive device in a bistable manner between a condition of zero impedance and a condition or normal characteristic impedance, said third terminal being connected to said second point and said fourth terminal being connected to said second terminal.

3. An electric circuit including a plurality of superconductive storage elements connecting in series between a first point and a second point, a superconductive device connected between a first terminal and a second terminal, means for applying an input signal to said device, said input signal acting to switch said device in a bistable manner between a condition of zero impedance and a condition or normal characteristic impedance, said first terminal being connected to said first point of the series connected superconductive storage elements and said second terminal being connected to said second point of the series connected storage elements, said superconductive storage elements and said superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane.

4. An electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a first superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second superconductive device connected between a third terminal and a fourth terminal, means for applying a second input signal to said second superconductive device, said second input signal acting to switch said second device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point, [said second terminal and] said third terminal being connected to said second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements and said first superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane.

5. An electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a first superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second superconductve device connected between a third terminal and a fourth terminal,

means for applying a second input signal to said second superconductive device, said second input signal acting to switch said second device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point, [said second terminal and] said third terminal being connected to said second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements and said first and second superconductive devices being constructed of thin films On a substrate which supports a thin superconductive ground plane, said second terminal being connected to the thin superconductive ground plane of said first superconductive device, said fourth terminal being connected to the thin superconductive ground plane of said second superconductive device.

6. In a storage matrix of a computer, the combination comprising: an electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a superconductive device connected between a first terminal and a second terminal, means for applying an input signal to said device, said input signal acting to switch said device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point of the series connected superconductive storage elements and said second terminal being connected to said second point of the series connected storage elements, said superconductive storage elements and said superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane, the normal characteristic impedance of the first and second superconductive devices being equal to the characteristic series connected storage elements.

7. In a storage matrix of a computer, the combination comprising: an electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a first supercon ductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second supercon ductive device connected between a third terminal and a fourth terminal, means for applying a second input signal to said second superconductive device, said second input signal acting to switch said second device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point, [said second terminal and] said third terminal being connected to said second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements and said superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane, a read circuit connected across said first and second terminals, a Write circuit connected across said third and fourth terminals, the first superconductive device being normally conducting and the second superconductive device being superconducting thereby short-circuiting the output of the write circuit during reading of the information stored in the storage elements, the first superconductive device being superconducting thereby short-circuiting the input of the read circuit and the second superconductive device being normally conducting during the writing of information in the storage device.

8. The combination of claim 7, wherein the normal characteristic impedance of the first and the second super-conductive devices is equal to the characteristic impedance of the line formed by the plurality of series connected elements.

9. An electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said device, said first input signal acting to switch said device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point of the series connected superconductive storage elements and said second terminal being connected to said second point of the series connected storage elements, said superconductive storage elements and said superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane, each storage element comprising a pair of parallel superconductive paths, means for applying a second input signal to each storage element, one of said paths being switched from the superconducting to the normally conducting state in response to said second input signal, information being stored in each storage element by setting up a persistent current to circulate around the loop formed by said pair of superconductive parallel paths.

10. A circuit as recited in claim 9, wherein each path of each pair of superconductive parallel paths is composed of a different material, and the second input signal is applied to a superconductive conductor which is electrically isolated from the traverses a respective pair of parallel paths.

11. An electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a first superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second superconductive device connected between a third terminal and a fourth terminal, means for applying a second input signal to said second superconductive device, said second input signal acting to switch said second device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point, [said second terminal and] said third terminal being connected to said second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements, and said superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane, each storage element comprising a pair of parallel superconductive paths, means for applying a third input signal to each storage element, one of said paths being switched from the superconducting to the normally conducting state in response to said third input signal, information being stored in each storage element by setting up a persistent current to circulate around the loop formed by said pair of superconductive parallel paths.

12. A circuit as recited in claim 11, wherein each path of each pair of superconductive parallel paths is composed of a different material, and the third input signal is applied to a supeconductive conductor which is electrically isolated from and traverses a respective pair of parallel paths.

13. An electric circuit including a plurality of superconductive storage element connected in series between a first point and a second point, a first in line cryotron connected between a first terminal and a second terminal, means for applying a first input signal to said first in line cryotron, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second in line cryotron connected between a third terminal and a fourth terminal, means for applying a second input signal to said second in line cryotron, said second input signal acting to switch said second cryotron in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point, [said second terminal and] said third terminal being connected to said second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements and said in line cryotrons being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane.

14. In a storage matrix of a computer, the combination comprising: an electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a first superconductive device connected between a first terminal and a second terminal, means for applying a first input signal to said first superconductive device, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second superconductive device connected between a third terminal and a fourth terminal, means for applying a second input signal to said second superconductive device, said second input signal acting to switch said second device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, said first terminal being connected to said first point, [said second terminal and] said third terminal being connected to said second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements and said superconductive device being constructed of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being connected to said superconductive ground plane, each storage element comprising a pair of parallel superconductive paths, means for applying a third input signal acting to switch one of said paths from the superconducting to the normally conducting state, information being stored in a storage element by setting up a persistent current to circulate around the loop formed by said pair of superconductive parallel paths, a read circuit connected across said first and second terminals, a write circuit connected across said third and fourth terminals, the first superconductive device being normally conducting and the second superconductive device being superconducting thereby short-circuiting the output of the write circuit during reading of the information stored in the storage elements, the first superconductive device being superconducting thereby short-circuiting the input of the read circuit and the second superconductive device being normally conducting during the writing of information in the storage device.

15. A storage matrix as defined in claim 14, wherein the normal characteristic impedance of the first and the second superconductive devices is equal to the characteristic impedance of the line formed by the plurality of series connected elements.

16. An electric circuit including a plurality of superconductive storage elements connected in series between a first point and a second point, a first crossed film cryotron with multiple crossings connected between a first terminal and a second terminal, means for applying a first input signal to said first crossed film cryotron, said first input signal acting to switch said first device in a bistable manner between a condition of zero impedance and a condition of normal characteristic impedance, a second cross film cryotron with multiple crossings connected between a third terminal and a fourth terminal, means for applying a second input signal to said second crossed film cryotron, said second input signal acting to 1 l 1 2 switch said second crossed film cryotron in a bistable References Cited l between a condmon QQ Y 'mpedance and a The following references, cited by the Examiner, are condition normal t first of record in the patented file of this patent or the original terminal being connected to said first point, [sald second Pamntv terminal and] said third terminal being connected to sald 5 UNITED STATES PATENTS second point, and said fourth terminal being connected to said second terminal, said superconductive storage elements and said crossed film cryotrons being constructed TERRELL FEARS, Primary Examiner of thin films on a substrate which supports a thin superconductive ground plane, said second terminal being con- 10 US. Cl, X.R,

nected to said superconductive ground plane. 307238 3,135,946 6/1964 Miller 340'173.l 

